IEEE

Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting

Abstract: Formal Property Verification (FPV), using System Verilog Assertions (SVA), is crucial for ensuring the completeness of design with respect to the specification. However, writing SVA is a ...
IEEE

V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

Abstract: This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and ...